Toward multiple-bit-per-cell memory operation with stable resistance levels in phase change nanodevices
Published in IEEE Transactions on Electron Devices, 2016
Abstract
Resistance drift of the amorphous states of multilevel phase change memory (PCM) cells is currently a great challenge for the commercial implementation of a reliable multiple-bit-per-cell memory technology. This paper reports observation of a stable intermediate state for a multilevel PCM cell that is achieved through nonuniform heating with a square current injection top electrode. Drift coefficient of the intermediate state is an order of magnitude lower than reset and has weaker temperature dependence. Using finite-element simulations and an analytical model for the subthreshold current-voltage characteristics, based on thermally activated hopping of charge carriers across Coulombic donor-like traps, we conclude that the defect density is two orders of magnitude larger in the intermediate state. We attribute the low drift coefficient of the intermediate state to a large number of stable interfacial defects which dominate the electron transport. Current findings give way to a more stable ultrahigh-density PCM device.